1. Field of the Invention
The invention concerns a regenerator for transmitting digital signal frames including payload bits and justification bits, comprising extractor means to extract the digital signals from the incoming frames, reconstructor means including a memory in which said digital signals extracted from the incoming frames are stored temporarily and which is adapted to form from the digital signals stored in the memory frames to be transmitted under the control of an internal clock, and control means operating on said digital signals extracted from the incoming frame to compensate for differences between the clock under whose control the incoming frames were sent and the internal clock.
2. Description of the Prior Art
A regenerator of this kind is known from patent application WO88.07300. This type of regenerator is suitable for networks transmitting digital signals over long distances and in particular over microwave links.
In a digital transmission system the transmitter is often associated with plesiochronous multiplexing means and constructs a composite digital signal in the form of frames. Each frame conventionally comprises consecutive frame bits in the form of pulses sent by the transmitter at the send timing. The frame bits conventionally comprise payload bits, justification indication bits and at least one justification opportunity bit.
The regenerator known from the above-mentioned document is designed so that there is no accumulation of jitter between two nodes of a network. This jitter appears in the regenerators which send frames under the control of a clock derived from the clock under whose control the incoming frames were sent.
In this known regenerator the extractor module uses a phase-locked loop to derive a first clock from digital signals extracted from the received frames. The digital signals include the payload bits and the justification bits and are clocked into the memory by the first clock and clocked out from the memory by an internal clock to form regenerated frames. The reconstructor module is adapted to eliminate or add justification bits in the regenerated frames under the control of the control means to compensate for differences between the clock under whose control the regenerated frames are sent and the clock under whose control the incoming frames were sent. One problem experienced with this type of regenerator is that the regenerated frames are not necessarily the same size as the incoming frames because justification bits have been removed or added. It is then necessary to include in each regenerated frame an additional data field giving the number of justification bits in the frame. Moreover, this type of regenerator is not suitable for digital signal frames including justification bits including justification indicator bits and justification opportunity bits at fixed positions within each frame. With this type of frame it is not possible to reposition the justification bits in the reconstructed frame. Nor is it possible to reduce or increase the frame size. What is more, some justification opportunity bits may be wanted data bits. Therefore these justification opportunity bits cannot be eliminated to compensate differences between the clock under whose control the incoming frames were sent and the clock under whose control the regenerated frames are sent.
An object of the invention is to remedy the above-mentioned drawbacks by proposing a regenerator in which jitter does not accumulate, which does not include any phase-locked loop and which is suitable for frames including justification indicator bits and justification opportunity bits.